The present invention relates to delta-sigma analog-to-digital converter devices and methods, and in particular to means for measuring the duty cycle of a delta-sigma analog-to-digital converter device.
A device for converting an analog signal to a digital signal for processing by a digital computer is an analog-to-digital (A/D) converter that uses a pulse width modulator type quantizer, which produces a pulse train having a duty cycle that is proportional to the input analog signal level, followed by means to measure the duty cycle over some time period of interest. A known method for implementing a pulse width modulator is the delta-sigma (xcex94-xcexa3) quantizer, detailed in FIG. 3 and discussed below.
Delta-sigma analog-to-digital (xcex94-xcexa3 A/D) converters are a class of A/D converters characterized by use of the extremely simple xcex94-xcexa3 quantizer design. The quantizer within a xcex94-xcexa3 A/D converter provides an output signal having only one bit of resolution. To achieve higher resolutions, many sequential output samples from the quantizer are averaged or processed by other digital means. The primary advantage of xcex94-xcexa3 A/D converters is their analog simplicity which makes them exceptionally linear, small, and insensitive to component tolerance variations so that they are easy to integrate within a mostly digital integrated circuit.
Prior art xcex94-xcexa3 A/D converters are characterized by feeding a source of analog information into a xcex94-xcexa3 A/D quantizer that converts the analog data into a xe2x80x9cdensityxe2x80x9d modulated serial digital data stream, and subsequent digital signal processing of that data to arrive at a meaningful output. The xcex94-xcexa3 A/D quantizer includes one or more stages of analog integration, which corresponds to the xe2x80x9corderxe2x80x9d of the quantizer. This is followed by a digital delay stage, typically, a latch, which provides the output from the quantizer as well as a portion of the feedback signal for the quantizer.
FIG. 1 is a block diagram of a generic prior art xcex94-xcexa3 A/D converter implementation at a system level. The analog input signal that is applied to input terminal 1 of the xcex94-xcexa3 A/D converter consists of both AC and DC components. A xcex94-xcexa3 quantizer 3 receiving the analog input signal may be of any order and may possess either a conventional linear or non-linear (as in high information delta modulation xe2x80x9cHIDMxe2x80x9d and adaptive delta modulation) transfer function, wherein the order is defined as the number of integrators embedded within the xcex94-xcexa3 A/D quantizer block 3. The output of the xcex94-xcexa3 A/D quantizer is shown on line 5 as a 1-bit serial digital data stream having an output that is substantially xe2x80x9cdensityxe2x80x9d modulated and is proportional to the product of the input signal at 1 and the transfer function operated by the xcex94-xcexa3 A/D quantizer 3.
The output 5 of the quantizer 3 in prior art xcex94-xcexa3 A/D converters has been processed in a number of ways, including decimation, averaging, and digital filtering to arrive at a usable signal. These methods have been used in various combinations and have been combined with weighting of the decimated samples and dithering to improve the resolution attainable (and hence the ultimately realizable accuracy and signal-to-noise ratio) and conversion speed. As illustrated in FIG. 1, the output 5 of the xcex94-xcexa3 A/D quantizer block 3 is accordingly input to a signal processing stage 7 that may include a decimation block 9, a weighting block 11, and one or both of a digital finite impulse response (FIR) filter 13 and infinite impulse response (IIR) filters 15 to reduce the raw xcex94-xcexa3 A/D quantizer""s serial output data to produce a high resolution output on line 17. Although there are many advantages to implementing the xcex94-xcexa3 A/D conversion process over more conventional A/D conversion processes, such as flash and successive approximation, many of the prior art methods of xcex94-xcexa3 A/D conversion unfortunately suffer from a much longer data latency than can be tolerated in many applications, most notably in control systems.
FIG. 2 illustrates waveforms typical of those produced by the prior art xcex94-xcexa3 A/D quantizer block 3 when a sinusoidal analog signal is applied to input terminal 1 and a high frequency clock is applied to a digital delay on input line 19, as discussed in FIG. 3. As the analog input signal represented as waveform 21 changes, the duty cycle of the pulse train from the xcex94-xcexa3 A/D quantizer block 3, i.e., the duty cycle of the xe2x80x9cQxe2x80x9d output from D-flip-flop shown at 22 in FIG. 3, which is represented in FIG. 2 as waveform 23, follows the input waveform 21. As shown by the portion of the pulse train enclosed by bracket 25, the xcex94-xcexa3 A/D quantizer""s serial output data on line 5 has a low short-term duty cycle over the interval, whereby it matches the sinusoidal input waveform 21, which is shown just below the bracketed portion 25, while the short-term duty cycle is higher over the bracketed interval 27, whereby it again matches the input waveform 21.
As set forth in the heretofore published literature, the output data from prior art xcex94-xcexa3 A/D quantizer has been processed in several different ways. The attempt of all these known methods has been to reduce the raw xcex94-xcexa3 A/D quantizer""s serial output data in a manner which can discern the finest incremental step size in the shortest period of time at point 17 in FIG. 1. In telecommunications parlance, this equates to maximizing the frequency response and dynamic range of the conversion process while maintaining a given minimum signal-to-noise ratio.
The methods by which such output data has been manipulated to achieve these goals are summarized here. Averaging over time is the simplest method for reducing the output bit stream from a xcex94-xcexa3 A/D quantizer. Accordingly, the number of HIGH or xe2x80x9c1xe2x80x9d states (see FIG. 2, number 29) of the xcex94-xcexa3 A/D output waveform 23 are xe2x80x9ccountedxe2x80x9d during a fixed measurement interval or time period, such as interval 31. A ratio of the total time spent in the xe2x80x9c1xe2x80x9d state to the fixed measurement interval 31 equates to the average duty cycle measured over that interval. The resolution of this method is limited to 1/d, where d is the number of clock cycles 33 contained within the fixed interval 31.
Increasing the measurement period 31 and increasing the ratio of measurement time to clock period to improve resolution results in a correspondingly longer net conversion time, which worsens latency. Increasing the clock frequency (waveform 33) to improve the resolution is limited by the performance of an integrator portion of the xcex94-xcexa3 A/D quantizer. Other secondary effects due to parasitic circuit elements also appear as the clock rate is increased.
A running average method for reducing the output bit stream from the xcex94-xcexa3 A/D quantizer adds many low resolution measurements together. This method concatenates together many contiguous lower resolution measurements to produce data that is similar to an average-over-time measurement, as described above, having an equal overall period.
The running average method can be combined with a small dither signal 35, as illustrated in FIG. 1, that is input through a mixer 37 to the basic average-over-time data reduction scheme described above. This method improves the resolution, but the dither must be filtered out.
The running average method can also be combined with a digital filter, which has been widely used to reduce the output data 5 from the xcex94-xcexa3 A/D quantizer 3. The digital filter following the running average reduces both the duty cycle or xe2x80x9cdensityxe2x80x9d and inter-bit phasing information contained in the xcex94-xcexa3 quantizer output 5 in order to achieve an output on line 17 having a given precision and minimal latency, as compared to the previously mentioned prior art methods. This method is commonly implemented as multiple stages of accumulation combined with decimation at block 9 and one or both of the digital FIR filter 13 and the IIR filters 15 within the signal processing block 7. This method has the advantage of providing very high resolution; however, the latency, i.e., time delay, of the output data at 17 from the analog input stimulus at xe2x80x9c1xe2x80x9d can be excessive for control systems applications. This long latency can be overcome by shortening the filter functions, particularly the typically long latency FIR block 13; but this degrades resolution, and, hence, the signal-to-noise ratio. Alternatively, the frequency of the xcex94-xcexa3 quantizer can be increased, but this reaches hardware limitations, as described above in the average-over-time measurement method. The running average and digital filtering method is often combined with multiplying each input to the digital FIR filter 13 by a time-varying weighting coefficient as represented by block 11. This weighting is a multiplicative process, in contrast to the analog xe2x80x9cditherxe2x80x9d method, which is an additive process.
U.S. Pat. No. 5,245,343, entitled Enhanced Accuracy Delta-Sigma A/D Converter, which is assigned to the assignee of the present application and is incorporated in its entirety herein by reference, provides an adaptive window-based decimation cycle whose exact timing is data dependent. The adaptive windowing process is implemented in a microprocessor-based signal processor and allows the first occurrence of a proper polarity state transition occurring during a window period to become the termination point of the computation cycle, rather than providing a fixed time interval. By doing so, the effective resolution is increased by an order of magnitude for a predetermined duty cycle.
As described by U.S. Pat. No 5,245,343, the xcex94-xcexa3 A/D quantizer 3 of the prior art typically includes a first operational amplifier having the analog input to be converted applied to either its non-inverting input or its inverting input and a reference voltage applied to the second input. A feedback capacitor couples the output of this operational amplifier back to the input having the analog input such that the combination functions as an analog integrator. The output of the integrator circuit is effectively coupled to the data input of a D-flip flop which is clocked at a predetermined rate. When the output from the integrator exceeds the threshold established for the D-input of the flip-flop, a logical xe2x80x9c1xe2x80x9d output will appear at its output terminal at the time that a clock signal is applied to the clock input of that flip-flop. The output from the flip-flop is a serial digital data output stream that is also effectively applied to the second input of the op-amp integrator.
FIG. 3 illustrates a simple, first-order linear xcex94-xcexa3 A/D quantizer 3 of a type well-known in the prior art. The xcex94-xcexa3 A/D quantizer 3 receives an analog input signal from a source 39 of analog information to an integrator 41 formed of an operational amplifier 43 and a feedback capacitor 45. The integrator circuit 41 is configured for operation either in an inverting mode or in a non-inverting mode (shown) having the analog input to be converted applied to its inverting input and a reference voltage VREF applied its non-inverting input. High and low reference voltages V+ and Vxe2x88x92 are coupled through a feedback resistor 47 to the non-inverting input of the operational amplifier 43. An electronic switch 49 is provided for switching the feedback resistor 47 between the two reference potentials V+ and Vxe2x88x92. A comparator 51 is coupled to receive the output of the integrator circuit 41 to provide threshold detection capability. The comparator 51 may be either a real component as illustrated or a xe2x80x9cpseudoxe2x80x9d component where its function is implemented by the input switching threshold of the data input xe2x80x9cDxe2x80x9d to the D flip-flop 53 controlled by a high frequency clock signal applied to the clock input on input line 19 and functioning as a digital delay.
As described by U.S. Pat. No. 5,245,343, an additional D flip-flop latch 55 may be included to form a multi-stage shift register 57, operating as a digital delay line in the circuit, coupled to receive as its input the output from the integrator circuit 41. The serial digital output signal train from the shift register is fed back to the input of the integrator circuit 41 and because of the frequency division which takes place, for a given high clock rate, the operational amplifier 43 may be of type having a lower gain/bandwidth product than in other prior art circuits.
FIG. 4 is a plot of signal waveforms over time at various points in the circuit for the case of the single clocked digital delay feed back to the integration phase, wherein the xcex94-xcexa3 A/D quantizer circuit includes only the single D flip-flop latch 53 for receiving the output from the integrator circuit 41. The clock waveform is shown at 59. The output of the flip-flop is shown on line 61 and the output of the integration stage is shown on line 63. Transitions of the flip-flop output signal 61 occur simultaneous with rising edges of clock signal 59. The slewing behavior of waveform 63 can be considered the base line for the prior art of the type having a single D flip-flop 53 in the xcex94-xcexa3 A/D quantizer circuit. The signal processor 7 takes the serial data output signal 61 of the single latch 53 and determines the digital form of the analog input signal.
FIG. 5 shows plots of signal waveforms over time at various points in the circuit for the case of the single clocked digital delay feed back to the integration phase, wherein the xcex94-xcexa3 A/D quantizer circuit includes the multi-stage shift register 57 coupled to receive as its input the output from the integrator circuit 41. Digital signal waveform 65 represents the system clock, which is applied to the clock terminal 41 of the latches 53, 55 of the multi-stage shift register 57. The system clock is shown as having a 50% duty cycle clock. A second waveform 67 on the graph of FIG. 5 represents the output of the downstream latch 55 on line 45. The output of the latch switches between the xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d states in response to the output of the integrator 41. Triangular waveform 69 represents the integrator output which is slewing in a triangular waveform in response to the input to the integrator circuit 41 on line 46, the feedback of the capacitor 49 and the operation of the multi-stage shift register 57. The signal processor 7 reads the serial output data signal 67 for determining the digital form of the analog input signal.
As illustrated in FIG. 5, during the high output of the latch 55, the integrator 41 is discharging until such time that the latch 55 changes state to a xe2x80x9c0xe2x80x9d and the integrator starts charging. As the analog input signal increases, the duration of time that the latch is at a xe2x80x9c0xe2x80x9d state also increases. When the input signal is at a maximum value, the output of the latch is maintained at a xe2x80x9c0xe2x80x9d state for the longest period. During the middle of the swing of the sinusoidal input signal, the output of the latch is in the xe2x80x9c0xe2x80x9d state and the xe2x80x9c1xe2x80x9d state an equal amount of time.
Thus, when the pulse width modulator is implemented as one of the xcex94-xcexa3 modulators shown in FIG. 3, the input analog signal level, VIN, is approximated by measuring the duty cycle over a sampling interval, Ts, where the sampling interval begins and ends on a clock transition (CLK). In other words, the signal processor must be able to count the number of highs for any sample period and calculate the duty cycle during a sample window.
An important characteristic of any means for converting an analog signal to a digital signal is the quantization error, which is the difference between the input analog signal and its digital representation. Since a digital signal can only take discrete values and an analog signal can take any value along a continuum, a quantization error is always present in the conversion process. When the xcex94-xcexa3 modulator circuit is used as shown in FIG. 3, the quantization error, assuming ideal components, is given by:             Q      1        =                            (                                    V              +                        -                          V              -                                )                ⁢                  T          CLK                            2        ⁢                  3                ⁢                  T          S                                q      1        =                  Q                              V            +                    -                      V            -                              =                        T          CLK                          2          ⁢                      3                    ⁢                      T            S                              
where TCLK is the time between clock transitions.
Measuring the duty cycle as described above can be accomplished by a counter for counting the number of highs and lows during any sample period. The counter is connected to the output of the xcex94-xcexa3 modulator circuit shown in FIG. 3 and is clocked with the same clock signal CLK; the counter is then sampled by the processor at the end of each sampling interval, TS. This method requires the same clock signal to be available both at the xcex94-xcexa3 modulator and at the counter to coordinate the counter with the sampling interval.
Accordingly, the devices and methods of the present invention reduce the quantization error resulting from differences between the periods of the xcex94-xcexa3 quantizer clock TCLK1 and the counter clock TCLK2 by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the circuit of the present invention is particularly effective for measuring the duty cycle of a pulse train from a xcex94-xcexa3 A/D converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the xcex94-xcexa3 modulator and the counter.
The invention is embodied by example and without limitation in a pulse-width modulator device that is illustrated in FIG. 7.
According to one aspect of the invention, the invention provides a delta-sigma modulator for an analog-to-digital converter for converting an analog voltage signal to a digital output signal, the delta-sigma modulator having an input for receiving the analog voltage signal; a first clock generator for generating a first clock signal at a first frequency; a pulse-width modulator-type quantizer that is responsive to an input analog voltage signal and to the first clock signal for producing a pulse train having a duty cycle that is proportional to the analog voltage signal level; a second clock generator for generating a second clock signal at a second frequency; a measuring mechanism that is responsive to the second clock signal for measuring the duty cycle of the pulse train over a sampling interval and outputting a density modulated serial digital data stream; and a signal processing stage for digitally processing the density modulated serial digital data and producing a digital output signal corresponding to the analog voltage signal.
According to another aspect of the invention, the pulse train output by the pulse-width modulator-type quantizer also has a plurality of pulses each having a rising edge and a,trailing edge, timing of the rising edge of each pulse being controlled by the first clock signal and timing of the trailing edge of each pulse being controlled by the analog input signal level.
According to another aspect of the invention, the frequency of the first clock signal is selected to be a submultiple of the frequency of the second clock signal.
According to another aspect of the invention, the signal processing stage of the invention is responsive to a third clock signal for timing the sampling interval over which the measuring mechanism measures the duty cycle of the pulse train, the third clock signal being generated at a third frequency that is a submultiple of the frequency of the first clock signal.
According to another aspect of the invention, the measuring mechanism is an asynchronous counter mechanism.
According to still other aspects of the invention, the invention provides a delta-sigma modulator for an analog-to-digital converter, including: (a) a source of time-varying analog signals; (b) a switch circuit having two reference input terminals, a control terminal, and an output terminal, such that the output terminal is connected to one of the input terminals based on the logic state of the control terminal; (c) a signal integrating circuit having an input terminal and an output terminal, the source of analog signals being coupled to the input terminal and producing at the output terminal a changing output signal proportional to the integral of the analog signals; (d) a clocked resettable D flip-flop circuit having a clock input terminal, a reset input terminal and an output terminal, the reset input terminal of the flip-flop circuit being connected to the output terminal of the signal integrating circuit, the flip-flop circuit being structured to change state as a function of a charge state of the integrating circuit; i.e., the flip-flop circuit is structured to change to the logic xe2x80x9c0xe2x80x9d whenever the signal input terminal is in the logic xe2x80x9c1xe2x80x9d state, and to change to the logic xe2x80x9c1xe2x80x9d state synchronous with a rising edge on the clock input terminal if the signal input terminal is in the logic xe2x80x9c0xe2x80x9d state; (e) a single feedback path coupling the output terminal of the flip-flop circuit to the control terminal of the switch circuit; (f) a counter circuit having a clock input terminal, a signal input terminal and an output terminal, the signal input terminal of the counter circuit being connected to the output terminal of the D flip-flop circuit for counting a quantity of state changes of the D flip-flop circuit during a sampling period; and (g) means for applying a plurality of different regularly occurring clock pulses to each of the clock input terminals of the D flip-flop circuit and the counter circuit, the clock pulse being applied to the counter circuit having a period that is a submultiple of a period of the clock pulse being applied to the D flip-flop circuit, and the period of the clock pulse being applied to the D flip-flop circuit being a submultiple of the sampling period.
According to another aspect of the invention, wherein the signal integrating circuit is a first-order signal integrating circuit, the clocked flip-flop circuit is a single Dflip-flop latch, and the counter circuit is an asynchronous counter circuit.
According to another aspect of the invention, wherein the delta-sigma modulator also includes a signal processor circuit having a signal input terminal and an output terminal, the signal input terminal of the signal processor circuit being connected to the output terminal of the counter circuit for sampling an output of the counter circuit at an end of each sample period.
According to yet other aspects of the invention, the invention includes methods for using an electronic circuit to convert an analog input signal to a digital output signal, one of the methods including: (a) receiving an analog input signal a source of time varying analog signals; (b) with the electronic circuit, receiving first and second clock signals at different frequencies, the frequency of the first clock signal being a submultiple of the frequency of the second clock signal; (c) with the electronic circuit, in response to the first clock signal using a delta-sigma modulation-type quantizer circuit for quantizing the analog input signal; and (d) with the electronic circuit, in response to the second clock signal, counting a number of highs occurring during a sample period.
According to another aspect of the method of the invention, the first clock signal is a submultiple of the sampling period.
According to another aspect of the method of the invention, quantizing the analog input signal includes producing a pulse train having a duty cycle that is proportional to the analog input signal level.
According to another aspect of the method of the invention, counting a number of highs occurring during a sample period includes measuring the duty cycle of the pulse train over the sample period.
According to another aspect of the invention, the method of the invention includes, with the electronic circuit, generating the first and second clock signals, and synchronizing the second clock signal with the first clock signal.
According to another aspect of the invention, the counting portion of the method of the invention includes, with the electronic circuit, outputting a signal representative of the number of highs counted during the sample period, and processing the signal representative of the number of highs counted during the sample period for converting the received analog input signal to a digital output signal.